Bipolar transistors are often used in a state of saturation. In this state, in some integrated circuits, parasitic transistors become active and may cause undesirable effects in the operation of the principal transistor.
FIG. 1 illustrates a typical NPN transistor element 8 manufactured according to a complementary bipolar process. An example of such a circuit and a method for making it is disclosed in U.S. Pat. No. 4,969,823 and 5,065,214, which are hereby incorporated by reference. This transistor element is typically formed on an N-type substrate 10. On the substrate 10, a P-well 12 is formed. In the P-well 12, an N-type subcollector 16 is formed. An N-type region 14 is also formed to make part of a junction isolation band for isolating from one another multiple devices on an integrated circuit. A P-type epitaxial layer 13 is formed on the N-type region 16, P-well 12 and substrate 10. In the epitaxial layer 13, an N-type region 15 is formed to make the collector of the transistor. This region 15 extends to the N-type sub-collector 16. A contact 11 is provided for this collector also. Another N-type region 17, extending to region 14 completes the junction isolation band. A P-type diffusion region 18 is formed in region 15 to form the base of the transistor. A contact 19 is also provided for the base. An N+ type region 20 is formed in region 18 to make the emitter of the transistor.
Other processes and structures may result in an integrated circuit construction in which the present invention suitably may be used. Such structures include NPN or PNP transistors formed in P-type or N-type layers, respectively. These layers, for multiple circuit elements on an integrated circuit are isolated, respectively, by N-type or P-type junction isolation bands.
A conventional transistor such as shown in FIG. 1 may be understood schematically by the diagram of FIG. 2 where it will be seen to comprise a principal transistor 22 as well as two parasitic transistors 29 and 34. The parasitic transistors are undesired but are a consequence of the way the principal transistor is formed. The principal transistor 22 has as its base 23, region 18; as its collector 24, regions 15 and 16; and as its emitter, region 20. Each region has an associated parasitic resistance, modelled by the resistive elements bearing reference numerals 26, 27A and 27B, and 28, respectively. When the principal transistor 22 goes into saturation, a parasitic vertical PNP transistor (the first parasitic transistor) 29 becomes active. Its base 30 is formed by collector regions 15 and 16 (FIG. 1); its collector 31 is formed by the epitaxial layer 13 and P-well 12 (FIG. 1) and its emitter 32 is formed by base region 18 (FIG. 1). The collector of this parasitic transistor 29, i.e., P-type epitaxial layer 13 and P-well 12 (FIG. 1), has associated with it a parasitic resistance 33 (FIG. 2).
A second parasitic lateral NPN transistor 34 may also become active. Its base 35 is formed by the P-type epitaxial layer 13 and P-well 12 (FIG. 1); its collector 36 is the N-type substrate 10 and isolation bands 14 and 17 (FIG. 1); and its emitter 37 is the N-type collector regions 15 and 16 (FIG. 1).
A transistor having the structure as shown in FIG. 1 is often used in a circuit which may be understood schematically by the diagram of FIG. 3. The transistor element 8 is enclosed by an outline box in FIG. 3. This circuit further includes a transistor 38 having a collector 41 connected to a high potential supply (Vcc) rail 39, a base 40 for receiving a drive current I.sub.DRIVE from a current source 43, and an emitter 42 connected to provide a current I.sub.B to the base 23 of the principal transistor 22. A load resistor 44 is also provided and connected between the supply rail 39 and the collector 24 of the principal transistor 22, supplying current I.sub.BIAS. A current source 46 is provided electrically in parallel with the base-emitter junction of the principal transistor 22. Both the emitter 25 and the P-type epitaxial layer 13 are connected to ground. The collector 36 of the second parasitic transistor 34 (formed by N-type substrate 10) is connected to supply rail 39 to receive the source voltage.
When the principal transistor 22 saturates, the first parasitic transistor 29 turns on. If, thereafter, the current I.sub.B driving the transistor element 8 is increased, the current flowing through the first parasitic transistor 29 increases. This current also flows through the parasitic resistance 33, causing the voltage across that resistance to increase. As this voltage increases, the voltage at the base 35 of the second parasitic transistor 34 eventually may become higher than the saturation voltage at the collector of the principal transistor 22 (which is also the emitter 37 of the second parasitic transistor 34) such that the base-to-emitter junction of transistor 34 becomes forward-biased. Thus, the second lateral parasitic transistor 34 may turn on. Because the collector 36 (i.e., the junction isolation bands 14, 17 and the substrate 10) of the second parasitic transistor must be connected to the supply rail 39 (to provide isolation), current then flows through the second parasitic transistor 34.
The carriers which flow through the second parasitic transistor 34 must be supplied to its emitter 37 via the collector of the principal transistor 22. The increased current through the parasitic resistance 28 and parasitic resistance 27A causes the collector-to-emitter voltage of transistor 22 to increase. The current in the second parasitic transistor 34 increases exponentially with an increase in current flowing through the parasitic resistance 33, which in turn increases approximately linearly with the current I.sub.B driving the base 23 of the principal transistor 22. Therefore, as the principal transistor 22 is driven deeper into saturation by a further increase in I.sub.B, the collector-to-emitter voltage begins to increase substantially when the second parasitic transistor 34 turns on. This increase is known as phase inversion, and may have deleterious effects in a circuit, especially a feedback circuit. For instance, if a feedback system is designed to increase a drive current in response to an increase in V.sub.CE (in order to reduce V.sub.CE), this system would work until phase inversion occurs. When phase inversion occurs, an increase in the drive current causes an increase in V.sub.CE.
To verify that phase inversion occurs in the manner described, the test circuit of FIG. 4 (similar to the circuit of FIG. 3) was used. The results of a test of this circuit are shown in FIG. 5 and described below.
In FIG. 4, the base 23 of principal transistor 22 is driven by a current source 48 to provide base current I.sub.B. I.sub.B was increased from 0 to 7 mA. V.sub.CE was measured with I.sub.BIAS set by current source 49 at, alternatively, 500 .mu.A or 250 .mu.A. The drive current I.sub.B is represented by units identified on the abscissa. The collector-to-emitter voltage V.sub.CE of the principal transistor 22 as a function of I.sub.B is represented by curves 1 and 2 in units identified on the left ordinate. With I.sub.BIAS set at 250 .mu.A, V.sub.CE is shown by curve 1; for I.sub.BIAS at 500 .mu.A, V.sub.CE is shown by curve 2. For reference, the current flowing through the parasitic resistance 33 is shown by curve 3 in units identified on the right ordinate. Also, for reference, the current flowing through the second parasitic transistor 34 is shown by curve 4 in units identified on the right ordinate. It readily can be observed that, as the base of the transistor 22 is driven with higher current, V.sub.CE attains a minimum at point 5 and starts increasing thereafter. The bottom of each of the curves 1 and 2 (i.e., its minimum) represents the points at which the second parasitic transistor 34 turns on. V.sub.CE begins to increase when the lateral second parasitic transistor 34 causes an increase in current flowing through the principal transistor 22.
For prior systems, the point at which phase inversion occurs cannot be predetermined, because the determining factors are process-dependent. Thus, systems are often designed for use so as to reduce the likelihood of phase inversion, by limiting the drive current. With this solution, however, the minimum attainable V.sub.CE is often higher than the minimum V.sub.CE which is actually attainable in the transistor. It is also impractical to design a system so that phase inversion is absolutely prevented. Such a design must handle all worst-case conditions, and may be unduly restrictive on normal operation.
Accordingly, it is an object of the present invention to allow activity of parasitic elements in a saturated bipolar transistor to be detected, thereby enabling prevention of phase inversion.
Another object of the present invention is to control the collector-to-emitter voltage of a saturated transistor.
It is another object of the present invention to minimize the collector-emitter voltage of a saturated transistor.